P-35: Barrier Layers for Poly-Si TFT Displays

摘要

A low temperature (≤620 ℃) poly-Si TFT process was developed to study the interaction between Code 1737 glass substrates, thin-film barrier layers, and semiconductor device structures fabricated on them. The barrier layers used in this study were 1100 A thick APCVD SiO_2 films. Results show that without a SiO_2 barrier layer, the leakage current of the top-gate poly-Si TFTs increased about two orders of magnitude after hydrogenation. This increase in leakage current is a direct result of the active channel being in intimate contact with the glass substrate, Study of the leakage current as a function of hydrogenation indicates that the leakage results from a back surface channel induced by the glass/Si interface states. Initial results also show that poly-Si TFTs fabricated on barrier coated glass substrates have: (1) lower leakage currents than those fabricated on either thermally oxidized Si or fused silica substrates, and (2) voltage shifts under bias less than those on oxidized c-Si or fused silica.