THE STUDY OF THE OPERATION LIMITATIONS OF THE EXISTING DRAM PACKAGES, TSOP II AND FBGA

摘要

Recently DDR has been replaced by DDR II to become the major player in the DRAM market. The corresponding package is also transferred from TSOP II to FBGA. However, there are TSOP II packages available on the market for DDR II which can run as high as 667MHz data rates which is much higher than the data rate of DDR, 400MHz, defined by JEDEC standards. Moreover, DDR III will replace DDR II in one or two years. One frequent asked question in the DRAM packaging houses is, “Can FBGA run for DDR III and beyond?” In this paper, both electrical characteristics of TSOP II and FBGA have been studied by simulation, then confirmed by electrical measurement using various conditions such as open, short, and through by choosing the extreme conditions of certain signal lines. The maximum clock rates for TSOP II and FBGA of 2GHz and 3GHz have been confirmed from both simulation and measurement results.