A CMOS-compatible, neuro-transistor array with monolithically-integrated circuit for studying cultured neuronal networks

摘要

In-plan microelectrode arrays have been proven to be useful tools for studying the connection and functions of neural tissues. But the number of electrodes is limited by the complex integration between sensors and signal-processing circuits. This paper presents a single-chip neural-electronic interface integrating the oxide-semiconductor filed effect transistors (OSFETs) with the signal-processing circuits. The chip is fabricated in the standard TSMC 0.35µm process, and then by die-level CMOS post process.