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TRANSISTORLESS ALL-MEMRISTOR NEUROMORPHIC CIRCUITS FOR IN-MEMORY COMPUTING

机译:用于内存计算的无晶体管全忆阻神经形态电路

摘要

A circuit for multiplying a number N of first operands each by a corresponding second operand, and for adding the products of the multiplications, with N ≥ 2; the circuit comprising: N input conductors; N programmable conductance circuits connected each between one of the input conductors and at least one output conductor; each programmable conductance circuit being arranged to be programmable at a value depending in a known manner from one of the first operands; each input conductor being arranged to receive from an input circuit an input train of voltage spikes having a spike rate that derives in a known manner from one of the second operands; and at least one output circuit arranged to generate an output train of voltage spikes having a spike rate that derives in a known manner from a sum over time of the spikes received on the at least one output conductor.
机译:一种电路,用于将N个第一操作数乘以相应的第二操作数,并将乘法的乘积与N相加≥ 2.该电路包括:N个输入导体;N个可编程电导电路,每个电路连接在一个输入导体和至少一个输出导体之间;每个可编程电导电路被布置为可编程,其值取决于第一操作数之一的已知方式;每个输入导体被布置成从输入电路接收电压尖峰的输入序列,该电压尖峰具有以已知方式从第二操作数之一导出的尖峰速率;以及至少一个输出电路,其被布置成产生电压尖峰的输出序列,该电压尖峰具有以已知方式从在至少一个输出导体上接收的尖峰随时间的总和导出的尖峰速率。

著录项

  • 公开/公告号EP3966745A1

    专利类型

  • 公开/公告日2022-03-16

    原文格式PDF

  • 申请/专利权人 HRL LABORATORIES LLC;

    申请/专利号EP20200801139

  • 发明设计人 YI WEI;CRUZ-ALBRECHT JOSE;

    申请日2020-03-06

  • 分类号G06N3/063;G11C11/54;G11C13;

  • 国家 EP

  • 入库时间 2024-06-14 22:48:30

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