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INTEGRATED CIRCUIT STRUCTURE WITH AVALANCHE JUNCTION TO DOPED SEMICONDUCTOR OVER SEMICONDUCTOR WELL

机译:集成电路结构,具有雪崩交界处与半导体井中的掺杂半导体

摘要

Embodiments of the disclosure provide an integrated circuit (IC) structure, including a doped well in a semiconductor substrate, in addition to a base region, emitter region, and collector region in the doped well. An insulative material is within the doped well, with a first end horizontally adjacent the collector region and a second end opposite the first end. A doped semiconductor region is within the doped well adjacent the second end of the insulative material. The doped semiconductor region is positioned to define an avalanche junction between the collector region and the doped semiconductor region across the doped well.
机译:本公开的实施例提供了一种集成电路(IC)结构,其包括在半导体衬底中的掺杂阱,除了掺杂阱中的基极,发射极区域和集电极区域之外。 绝缘材料在掺杂阱内,第一端水平地邻近集电区和第一端的第二端。 掺杂的半导体区域在邻近绝缘材料的第二端附近的掺杂阱内。 掺杂的半导体区域定位成在掺杂阱中限定集电区和掺杂半导体区域之间的雪崩结。

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