High throughput DRAM with distributed column access

摘要

An apparatus having memory dies with a memory cell array divided into a plurality of data segments. A stagger circuit selects a common command signal and sets a column access signal to select a data segment to be accessed based on the common command signal and/or an individual command signal to perform a memory operation corresponding to the selected common command signal on the selected data segment. A data bus connects the memory cell arrays to form data units with each data unit including a data segment from each memory cell array and configured such that the data segments are connected in parallel to the data bus and use a same line of the data bus. The stagger circuits are configured such that data segments identified for activation in the plurality of memory dies are not part of a same data unit.