For an output circuit with a double data rate operating dynamic random access memory (ddr dram), a with double data rate of operating a dynamic random access memory (ddr dram), a method for the clocked reading of data from at twice the data rate operating dynamic random access memory (ddr dram)

摘要

Output circuit (19) for a with double data rate operating dynamic random access memory (ddr dram), with:– a dll - circuit (32), which has an input of the for accepting an external clock signal (xclk) is configured,the dll - circuit (32) a first internal clock signal (dllf0) and a second internal clock signal (dllr0), and said first and second internal clock signal with the external clock signal (xclk) in predetermined time division holds neps are connected, and– a data - strobe - circuit (64) which, together with the dll - circuit (32) is connected, wherein the data - strobe - circuit (64) for providing a having a preamble data - - strobe signal (dqs) and for synchronizing the data - - strobe signal (dqs) and the preamble with the first and second internal clock signal (dllf0, dllr0) is configured,characterized in that– the first and second internal clock signal (dllf0, are interleaved dllr0), wherein the first and the second internal clock signals (dllf0, dllr0) are stable and mutually opposite logic states during all..