Wafer-level chip-scale package device with bump units configured to reduce stress-related failures

摘要

A wafer level chip scale package device (100) comprising: an integrated circuit chip (102, 312); at least a first array (126) of first bump units (128, 302) having on disposed on the integrated circuit chip (102, 312, 312), the first bump units (128, 302) comprising solder bumps (116, 352); andat least a second array (130) of second bump units (132,304) disposed on said integrated circuit chip (102,312), said second bump units (132,304) having solder bumps (116,360) and at least one copper (Cu) pillar (124, 338, 340), the first array (126) being near the center (134) of the integrated circuit chip (102, 312) and the second array ( 130) in areas near the edges (136) of the integrated circuit chip (102, 312), wherein bump units (132, 304) arranged in the second array (130) compared to bump units ( 128, 302) disposed in the first array (126) are subjected to increased stress levels due to mechanical or thermal forces when the integrated circuit chip (102, 312) is pushed over the bump units (128, 302, 132, 304 ) is attached to a printed circuit board (114), the solder bumps (116, 360) of the second contact h unit bumps (132, 304) are larger than the solder bumps (116, 358) of the first unit bumps (128, 302) to resist failure due to the elevated stress levels, and the at least one array (130) of second bumps - units (132, 304) configured to allow only mechanical attachment of the wafer level chip scale package device (100) to the printed circuit board (114).