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WAFER-LEVEL CHIP-SCALE PACKAGE DEVICE HAVING BUMP ASSEMBLIES CONFIGURED TO MITIGATE FAILURES DUE TO STRESS
WAFER-LEVEL CHIP-SCALE PACKAGE DEVICE HAVING BUMP ASSEMBLIES CONFIGURED TO MITIGATE FAILURES DUE TO STRESS
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机译:晶圆级芯片包装设备,具有凹凸不平的组件,可缓解因应力引起的故障
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摘要
Wafer-level chip-scale package semiconductor devices are described that have bump assemblies configured to mitigate solder bump failures due to stresses, particularly stresses caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having two or more arrays of bump assemblies for mounting the device to a printed circuit board. At least one of the arrays includes bump assemblies that are configured to withstand higher levels of stress than the bump assemblies of the remaining arrays.
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