Lateral power device with reduced on-resistance

摘要

Provides lateral power semiconductor devices with metal interconnect layouts for low on-resistance. The metal interconnect layout includes first, second and third metal layers, each layer including a source bar and a drain bar. The source bars of the first, second and third metal layers are electrically connected. The drain bars of the first, second and third metal layers are electrically connected. In one embodiment, the first and second metal layers are parallel and the third metal layer is perpendicular to the first and second metal layers. In another embodiment, the first and third metal layers are parallel and the second metal layer is perpendicular to the first and third metal layers. The non-conductive layer electrically connects the solder bumps to the source bar only or the drain bar only. As a result, there are multiple available paths, allowing the current to take any of the multiple available paths.