SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN DOPANT DIFFUSION BLOCKING SUPERLATTICES TO REDUCE CONTACT RESISTANCE AND ASSOCIATED METHODS

摘要

A semiconductor device (100) may include a semiconductor layer (101), spaced apart source and drain regions (102, 103) in the semiconductor layer with a channel region (130) extending therebetween, and at least one dopant diffusion blocking superlattice (125) dividing at least one of the source and drain regions into a lower region (104, 106) and an upper region (105, 107) with the upper region having a same conductivity and higher dopant concentration than the lower region. The at least one dopant diffusion blocking superlattice comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a gate (109, 110) on the channel region.