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BAYESIAN NEURAL NETWORK WITH RESISTIVE MEMORY HARDWARE ACCELERATOR AND METHOD FOR PROGRAMMING THE SAME
BAYESIAN NEURAL NETWORK WITH RESISTIVE MEMORY HARDWARE ACCELERATOR AND METHOD FOR PROGRAMMING THE SAME
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机译:贝叶斯神经网络具有电阻内存硬件加速器和编程方法
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摘要
The present invention concerns a Bayesian neural network (BNN) comprising an input layer (721), and, an output layer (723), and, possibly, one or more hidden layer(s) (722). Each neuron of a layer is connected at its input with a plurality of synapses, the synapses of said plurality being implemented as a RRAM array (711) constituted of cells, each column of the array being associated with a synapse and each row of the array being associated with an instance of the set of synaptic coefficients, the cells of a row of the RRAM being programmed during a SET operation with respective programming current intensities, the programming intensity of a cell being derived from the median value of a Gaussian component obtained by GMM decomposition into K Gaussian components of the marginal posterior probability of the corresponding synaptic coefficient, once the BNN model has been trained on a training dataset.;The present invention also concerns a method for programming such a Bayesian neural network after the BNN model has been trained on a training dataset.
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