Design Tradeoff of Internal Memory Size and Memory Access Energy in Deep Neural Network Hardware Accelerators

摘要

This paper analyzes the memory access amount in different data reuse schemes and internal memory sizes in order to design hardware deep neural network (DNN) accelerator with better power efficiency. After comparing the trade-off between memory energy consumption and SRAM sizes, we decide to design the accelerator using mixed input/output reuse schemes. Experimental results show that the numbers of DRAM access and SRAM access are reduced compared with state-of-the-art designs of similar designs for computation of the convolutional layers in the VGG-16 model.