DEFERRED SYNCHRONIZATION CIRCUIT AND CLOCK TRANSMISSION CIRCUIT

摘要

A deferred synchronization circuit (3) is constituted so as to comprise: a pulse synthesis circuit (11) for generating a synthesized signal that includes a first pulse signal synchronized to a reference signal and a second pulse signal synchronized to a feedback signal; a VCDL (12) for causing the synthesized signal generated by the pulse synthesis circuit (11) to be delayed and outputting a delayed signal that is the synthesized signal after being delayed; a pulse separation circuit (13) for generating a first separate signal synchronized with the first pulse signal included in the delayed signal outputted from the VCDL (12), and a second separate signal synchronized with the second pulse signal included in the delayed signal; a circulator (14) for outputting the first separate signal generated by the pulse separation circuit (13) to a clock receiving circuit (21) and thereafter outputting the first separate signal having been returned from the clock receiving circuit (21), as a feedback signal, to the pulse synthesis circuit (11); and a delay amount control circuit (15) for controlling the amount of delay of the synthesized signal by the VCDL (12) in accordance with a phase difference between the reference signal and the second separate signal generated by the pulse separation circuit (13).