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EFFICIENT INTER-CHIP INTERCONNECT TOPOLOGY FOR DISTRIBUTED PARALLEL DEEP LEARNING
EFFICIENT INTER-CHIP INTERCONNECT TOPOLOGY FOR DISTRIBUTED PARALLEL DEEP LEARNING
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机译:有效的芯片间互连拓扑,用于分布式并行深度学习
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摘要
The present disclosure provides a system comprising: a first group of computing nodes and a second group of computing nodes, wherein the first and second groups are neighboring devices and each of the first and second groups comprising: a set of computing nodes A-D, and a set of intra-group interconnects, wherein the set of intra-group interconnects communicatively couple computing node A with computing nodes B and C and computing node D with computing nodes B and C; and a set of inter-group interconnects, wherein the set of inter-group interconnects communicatively couple computing node A of the first group with computing node A of the second group, computing node B of the first group with computing node B of the second group, computing node C of the first group with computing node C of the second group, and computing node D of the first group with computing node D of the second group.
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