首页>
外国专利>
Combinatorial serial and parallel test access port selection in a JTAG interface
Combinatorial serial and parallel test access port selection in a JTAG interface
展开▼
机译:JTAG接口中的组合串行和并行测试访问端口选择
展开▼
页面导航
摘要
著录项
相似文献
摘要
A circuit includes a test data input (TDI) pin receiving a test data input signal, a test data out (TDO) pin outputting a test data output signal, and debugging test access port (TAP) having a test data input coupled to the TDI pin and a bypass register having an input coupled to the test data input of the debugging TAP. A multiplexer has inputs coupled to the TDI pin and the debugging TAP. A testing TAP has a test data input coupled to the output of the multiplexer, and a data register having an input coupled to the test data input of the testing TAP. The multiplexer switches so the test data input signal is selectively coupled to the input of the data register of the testing TAP so the output of the debugging TAP is selectively coupled to the input of the data register of the testing TAP.
展开▼