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Testing circuit, testing method, and apparatus for testing multi-port random access memory

机译:测试电路,测试方法和用于测试多端口随机存取存储器的装置

摘要

A testing circuit for testing a multi-port random access memory includes an input circuit, a first port testing circuit and a second port testing circuit. The input circuit receives a testing clock signal and a test mode enable signal and is configured to provide the testing clock signal according to the test mode enable signal. The first port testing circuit is coupled to the input circuit, and is configured to output a first word line enable signal for a first port of the multi-port random access memory according to the testing clock signal and a first delay signal. The second port testing circuit is coupled to the input circuit, and is configured to output a second word line enable signal for a second port of the multi-port random access memory according to the testing clock signal and a second delay signal. The first word line enable signal and the second word line enable signal are asserted at the same time, and the first word line enable signal is de-asserted before the second word line enable signal. A method adapted for a testing circuit and an apparatus including a device under test and a testing circuit are also introduced.
机译:用于测试多端口随机存取存储器的测试电路包括输入电路,第一端口测试电路和第二端口测试电路。输入电路接收测试时钟信号和测试模式使能信号,并且被配置为根据测试模式使能信号提供测试时钟信号。第一端口测试电路耦合到输入电路,并且被配置为根据测试时钟信号和第一延迟信号输出用于多端口随机存取存储器的第一端口的第一字线使能信号。第二端口测试电路耦合到输入电路,并且被配置为根据测试时钟信号和第二延迟信号输出用于多端口随机存取存储器的第二端口的第二字线使能信号。第一字线使能信号和第二字线使能信号同时被置位,并且在第二字线使能信号之前,第一字线使能信号被解除。还引入了一种适用于测试电路的方法和包括被测设备的装置和测试电路。

著录项

  • 公开/公告号US11037644B2

    专利类型

  • 公开/公告日2021-06-15

    原文格式PDF

  • 申请/专利权人 TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.;

    申请/专利号US201916561055

  • 发明设计人 HIDEHIRO FUJIWARA;YEN-HUEI CHEN;

    申请日2019-09-05

  • 分类号G11C29;G11C29/02;G06F11/27;G11C11/41;G11C8/16;G11C29/50;

  • 国家 US

  • 入库时间 2022-08-24 19:19:23

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