A method for vertically routing a logic cell incorporating a stacked transistor in a 3D logic device

摘要

The semiconductor device includes: a substrate having a substantially flat surface; A first logic gate provided on the substrate, comprising: a first field effect transistor (FET) having a first source-drain region pair and a first channel; A second logic gate stacked on the first logic gate along a vertical direction perpendicular to the surface of the substrate, the second logic gate including a second source-drain region pair and a second FET having a second channel. , A second logic gate; And a contact electrically connecting the source-drain region of the first FET to the source-drain region of the second FET so that at least a portion of the current flowing between the first and second logic gates flows along the vertical direction. .