TWO-SYSTEM-ON-CHIP (SOC) FOR THE PREPARATION OF HARDWARE VEHICLE OLERANCE (HFT) FOR A PREPARED SOC

摘要

Devices of systems providing security integrity level (SILs) and hardware error tolerance (HFT) include a first Die, the first Die comprehensively a first processing logic, associated with a first connection and the first connection associated with a second processing logic of a second This. The first may also include a second connection to an input/output (I/O) channel, the second being linked to the first processing logic. The devices may also include a second The, the second The comprehensively a second processing logic and a third connection of a secondary device,coupled with the second processing logic. The secondary device is located outside the system. The second processing logic is designed to select from three configurations based on signals from the second processing logic and secondary device: sending of first output data on the I/O output channel, sending of second output data on the I/O output channel, or turning off the I/O channel.