首页> 中文期刊> 《北京理工大学学报:英文版》 >Hardware-Software Co-Simulation for SOC Functional Verification

Hardware-Software Co-Simulation for SOC Functional Verification

         

摘要

A hardware-software co-simulation method for system on chip (SOC) design is discussed. It is based on an instruction set simulator (ISS) and an event-driven hardware simulator, and a bus interface model that is described in C language provides the interface between the two. The bus interface model and the ISS are linked into a singleton program--the software simulator, which communicate with the hardware simulator through Windows sockets. The implementation of the bus interface model and the synchronization between hardware and software simulator are discussed in detail. Co-simulation control of the hardware simulator is also discussed.

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