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MASKED MULTI-LANE INSTRUCTION HAVING BOTH FAST AND SLOW EXECUTION PATHS
MASKED MULTI-LANE INSTRUCTION HAVING BOTH FAST AND SLOW EXECUTION PATHS
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机译:屏蔽多车道指令具有快速和慢速执行路径
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摘要
A processor includes a load/store unit and an execution pipeline to execute an instruction that represents a single-instruction-multiple-data (SIMD) operation, and which references a memory block storing operand data for one or more lanes of a plurality of lanes and a mask vector indicating which lanes of a plurality of lanes are enabled and which are disabled for the operation. The execution pipeline executes an instruction in a first execution mode unless a memory fault is generated during execution of the instruction in the first execution mode. In response to the memory fault, the execution pipeline re-executes the instruction in a second execution mode. In the first execution mode, a single load operation is attempted to access the memory block via the load/store unit. In the second execution mode, a separate load operation is performed by the load/store unit for each enabled lane of the plurality of lanes prior to executing the SIMD operation.
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