IC PACKAGE DESIGN AND METHODOLOGY TO COMPENSATE FOR DIE-SUBSTRATE CTE MISMATCH AT REFLOW TEMPERATURES

摘要

An IC package including an integrated circuit die having a major surface and one or more solder bumps located on the major surface in at least one corner region of the major surface and a substrate having a surface, the surface including bump pads thereon. The major surface of the integrated circuit die faces the substrate surface, the one or more solder bumps are bonded to individual ones of the bump pads to thereby form a bond joint, the major surface of the integrated circuit die has a footprint area of at least about 400 mm². A ratio of a coefficient of thermal expansion of the substrate (CTE_sub) to a coefficient of thermal expansion of the integrated circuit die (CTE_die) is at least about 3:1. A method of manufacturing an IC package is also disclosed.