Improvements in or relating to Electronic Shift Registers.

摘要

1,154,673. Shift register. WALTHERBUROMASCHINEN G.m.b.H. 5 Jan., 1968 [5 Jan., 1967], No. 883/68. Heading G4C. An electronic shift register comprises means for selecting a predetermined number of adjacent positions at the input end of the register, the predetermined number being less than the total number of positions in the register, means for moving information from the predetermined positions as a group, when information is present in all said predetermined positions, from the input end of the register to predetermined positions at the output end of the register, and means for holding the group of information in the predetermined positions at the output end of the register whereby further information can be shifted into the cleared input end of the register without affecting the position in the register of the previously stored group of information. Data supplied from a keyboard 1 (Figs. 1, 2) passes through a four bit buffer stage A 0 to the first stage A 1 of the shift register A A start signal sets a flip-flop D which allows a pulse generator E to commence feeding pulses to a counter F and a gate G. The counter produces clear 5 and shift 6 pulses. Pulses from the gate pass to a shift control circuit B to effect a single step shift in A. When the control has worked through all the stages of A a stop signal is produced which resets flip-flop D and disables the pulse generator. Fig. 6 shows the circuit for automatically shifting groups of information. Tap a on counter R is preset to the number required in the group, e.g. 6. When the sixth signal has been fed in a signal generated by counter R appears at tap a and is passed to gate Q enabled by flipflop P indicating that groups of information are being dealt with, and by signal 4SP1/SP which indicates that read-out is not required. The signal from Q on line 3 causes the counter in Figs. 1, 2 to commence. When the group has reached the predetermined position a signal 8 is produced to stop the counter and is fed to AND gate S enabled by the no-read-out signal 4SP1/SP and the signal from flip-flop P. This causes flip-flop T to lock register division U, containing positions A5-A10 so that no further clearing or shifting can be produced in these stages. To read out data a signal on line 4 frees the block U 1 . Three shift control circuits are described (Figs. 3, 4, 5, not shown), in one circuit data from each stage is passed simultaneously via an AND gate enabled by coincident signals 5, 6 (Figs. 1, 2) to a delay connected to the next stage. At the same time the signals 5, 6 are applied to a shortest delay to cause resetting of each stage before the new data is received. In an alternate system the B counter (Fig. 1) enables AND gates only in the one stage and allows signal 5 first to reset the receiving stage and then a later signal 6 to enable AND gates to pass the data from the preceding stage. The third system has two input registers connected in series. Data is fed into register 2 from the keyboard and the contents of A 1 are fed to register 1. The B counter reads 1 so the contents of register 2 are fed to A 1 , the contents of register 1 to register 2 and A 2 to register 1. The B counter reads 2 so register 1 is fed to register 2 &c. thus shifting the contents of the A register along. When the last stage of the A register is reached a stop signal is produced.