MEMORY MAINTENANCE ARRANGEMENT FOR RECOGNIZING AND ISOLATING A BABBLING STORE IN A MULTIST ORE DATA PROCESSING SYSTEM

摘要

1326939 Data processing WESTERN ELECTRIC CO Inc 6 Oct 1970 [6 Oct 1969] 47390/70 Heading G4A A data processing system includes a number of stores 300-0, 300-n addressed over a common bus by a central processor and is arranged, on detection of an erroneous response over the bus resulting from addressing a predetermined location in an addressed store, each store containing at the predetermined location a unique identifying word, and to analyse the response to determine whether more than one identifying word has been received and thus whether more than one store is responding to the addressing. As described two central processors 200-1, and 200-2, e.g. as described in Specification 1,129,660, are provided, each being associated with a respective bus, BUS 0, and BUS 1. Corresponding stores on the respective buses contain identical data and are assigned the same identification word which consists of a single binary '1' in a field of '0's. Normally one of the processors is 'on line', e.g. controlling a telephone switching network, and the other is off-line. The stores-300 are of the magnetic twister type, each having a capacity of 2SP14/SP words each of which includes 40 data bits and 7 error check bits. The bus contains conductors 331 which provide a 4-bit OP code designating read, write etc. operations, 341 which provide the 40 data and 7 check bits, 351 which provide a 5 bit store identification code, and 361 which provide 14 bit addresses. Each store is assigned its unique 5-bit code by means of a permanent store 303, the received 5-bit word being compared with the wired in address in circuit 302. A match sets flip-flop 305 and enables gate 306 allowing the selected store to be addressed. The 5-bit word received by the store may be immediately retransmitted via gate 320 and register 311 for verification. Error checking operations-If data accessed from the store fails any error checks a wired in interrupt device stops the off line processor and initiates a fault recognition sequence which is stored in one of the stores 300. To ensure that the sequence is not executed from a failed store the processors switch buses except where the duplicate store containing the fault recognition sequence has previously been disconnected when no recovery is possible. The on-line processor then sets a binary '1' in a register at a position corresponding to the '1' in the identifying word of the addressed store. The identifying word of the addressed store is then accessed and exclusive-OR masked with the contents of the register. Any remaining '1' bit thus identifies a suspect store which is disconnected. The disconnection is achieved by resetting 'Port' flipflop 312 to block AND 313 and prevent the store transmitting data. The process is then repeated and if the masked word is not all binary '0's the addressed store is assumed to be faulty. The Specification sets out a fault recognition program in some detail and states that it may be used as a part of a larger testing program executed either in response to faults or as preventive maintenance.