The frequency divider circuit uses at least one counter circuit receiving the oscillator output and comprising a pseudo-statistical noise generator and a decoder state. A series circuit of flip flops is used to form the counter, with a control input of each flip-flop supplied with the frequency to be divided. The non-inverting output of each flip-flop is connected via an inverter to the output line of the divider. One or more flip-flop outputs are fed to the input of the first flip-flop via a logic gate.
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