In the pal system - - color image signal decoding circuit for color television receiver

摘要

1338010 Television SONY CORP 17 Feb 1972 [18 Feb 1971 1 April 1971] 7367/72 Heading H4F In a colour television receiver for receiving PAL type signals, the chrominance signals for alternate lines are selected by switch 20, Fig. 2, the switch alternately selecting said line and the one line period delayed replica of said line (e.g. a line sequence 1, 1, 3, 3, 5, 5) for passage to a demodulator 22 for detection with the output of C.W. oscillator 30. When the receiver is switched on it is equally probable that the switch 20 and controlling flip-flop 25 will lock on to and pass lines having the (R-Y) chrominance component lagging the (B-Y) component by 90 degrees and having a B- burst (Fig. 4), whereas the C.W. oscillator 30 may have a phase synchronized with a previous B + burst. The circuitry described detects the selection of such (B -) lines and incorrectly phased C.W. oscillator output, and produces a responding correction of the phasing of switch 20. In the P.A.L; E.B.U. Specification for the twitching burst field blanking, Figs. 1A, 1B, 1C, 1D, the last colour burst before, and the first colour burst after the burst blanking period, are B+ bursts and the first line having the B+ burst occurs after an inerval from the beginning of the vertical syn pulse V s , according to a 6, 5¢, 5, 6¢ line sequence. The first line having the B - burst correspondingly occurs after an interval from the beginning of the pulse V s according to a 7, 6¢, 6, 7¢ time sequence. The circuitry thus determines the interval from the beginning of the pulse V s to the start of the first line selected by the switch 20 for four successive fields and causes the rephasing of switch 20, if the 7, 6¢, 6, 7¢ sequence is detected. The leading edge of pulse V s , (Fig. 6A) therefore sets (58, Fig. 6E) a bi-stable circuit 55, Fig. 3, which is reset by the first of a series of square pulses 63, Fig. 6D, derived from the burst signals B+ (B-), Fig. 6B, 6C (burst gate 27, detector 47, amplifier tuned to half line frequency 46, squarer 49). The four pulses 58 from the four successive fields (58A, 58B, 58C, 58D, Fig. 5E) are converted by integrator 51 into corresponding ramp voltages, such that only with the higher valued sequence 7, 6¢, 6, 7¢, Figs. 5H, 5I, 5J, 5K, 5L, 5M, do the ramps 59H, 59I, 59J, 59K reach above a threshold and produce a pulse 61 for rephrasing the switch 20. A modification, involving the addition of a second bi-stable circuit is necessary (Figs. 9 and 10, not shown), if the circuitry is to lock to the B - lines.