Fault detection in addressing units - is effected by generating combinations and memorising faulty addresses in fault detector

摘要

Binary addressing units are employed in computer controlled telephone systems where there are a large number of repetitive equipments. Satisfactory operation of the address memory is effected by using a fault detector connected between the outputs of decoding circuits and the address inputs of the addressable memories. A fault detector (1) is connected to associated switching circuits and to the spacial address memory (2) whose output is controlled by the fault detector through the control unit (4) of the switching system. This unit contains the clock pulse generator (5) and control computer (6). Binary elements are transmitted via a register (7) to the inputs of multiplexers (8) in a matrix (3) with associated decoders (9). This enables a number of address combinations to be made, any faults are memorised in an addressable memory (10).