D-flip flop using integrated injection logic techniques - has surface area reduced by clocking set and reset over inverters

摘要

The I2L D-flip flop has the surface of its semiconductor material reduced by connecting the set input (S) as well as the reset input (R) over an inverter (V1, V2) to the clock input. The set input and the third input (3) of the second gate (G2) in the second memory cell (II) are electrically connected, as are teh reset input and the third input of the first gate (G1) in the second memory cell. There is no electrical connection between the set input and/or reset input and the inputs of the gates (G5, G6) in the first memory cell (I).