首页> 外国专利> Schottky junction integrated injection logic circuit - has buried layer within epitaxial layer on substrate with electrodes on adjacent zones

Schottky junction integrated injection logic circuit - has buried layer within epitaxial layer on substrate with electrodes on adjacent zones

机译:肖特基结集成注入逻辑电路-在衬底的外延层内具有掩埋层,电极在相邻区域上

摘要

The integrated injection logic arrangement is for Schottky I2L gate with a load transistor followed by an output transistor. The collector of the former is connected to the base of the latter, which has its collector connected to three Schottky diodes, each followed by an output terminal. An n+ doped silicon substrate (10) has an epitaxial layer (102) and between them is a doped deeply implanted layer (108). This forms the base of the output transistor, and the epitaxial layer above the deeply implanted layer forms the collector region, while the part below forms the emitter region. Portions of the emitter form a lateral load transistor, with an electrode (121) above it, for an input.
机译:集成注入逻辑装置用于肖特基I2L门,其负载晶体管后面是输出晶体管。前者的集电极连接到后者的基极,后者的集电极连接到三个肖特基二极管,每个二极管后接一个输出端子。 n +掺杂的硅衬底(10)具有外延层(102),在它们之间是掺杂的深注入层(108)。这形成输出晶体管的基极,深注入层上方的外延层形成集电极区,而下方的部分形成发射极区。发射极的部分形成横向负载晶体管,在其上方具有用于输入的电极(121)。

著录项

  • 公开/公告号DE2642210A1

    专利类型

  • 公开/公告日1978-03-23

    原文格式PDF

  • 申请/专利权人 SIEMENS AG;

    申请/专利号DE19762642210

  • 发明设计人 MUELLERRUEDIGERDR.-ING.;

    申请日1976-09-20

  • 分类号H01L27/06;H01L29/64;

  • 国家 DE

  • 入库时间 2022-08-22 22:00:41

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