Digital signal de-multiplexing circuit - has clock generator producing at least two clocks of identical frequency controlling incoming data rate and memory read rate

摘要

A numerical signal demultiplexing circuit is connected to a multiplexed signal path consisting of a whole number (a) of channels. The channels are received by respective ones of n memory devices into which incoming data is clocked by a clocking pulse rate identical to the received binary bit rate (F). The memories are read under the control of a second clock of identical frequency. The circuit is characterised by a signal generator delivering at least two clocking signals of identical frequency (F). Each memory has an associated numerical comparator comparing the two clocks and controlling the advanced or retard of an output pulse train to control generation of a finally adopted memory read clock.