Planar silicon-on-sapphire integrated circuits and method for producing such integrated circuits

摘要

Planar conductor-insulator-semiconductor (CIS) integrated circuits e.g. comprising complementary transistors 12, 14 built on an insulating substrate 16, such as sapphire or spinel, employ conductive polycrystalline silicon gates 24, 34. In order to provide devices having low leakage currents an oxidation temperature of less than 1000 DEG C is used to produce both the field oxide 38 and the gate oxide 26, 36. In addition, ion implantation techniques are used for doping the sources 18, 28 and drains 20, 30 of the transistors 12, 14 to provide close control over their doping concentrations. Utilization of N+ doped polycrystalline silicon gates allows phosphorus doped silicon dioxide 39 to be used as a getter, and also provides higher conductivity gates than P+ doped gates. IMAGE