Decoding circuit for dynamic semiconductor memory - has control circuit with input lateral MOSFET and several lateral and vertical MOSFETs and has specified terminal connections

摘要

The decoding circuit has several address transistors connected to form a NOR-gate. An activation transistor is used for switching a clock pulse line, while a separating transistor is incorporated between the activating transistor and the word line. A control network (ST) contains a lateral input MOS FET (T2), a laterial control MOS FET (T3) a vertical FET second control transistor (T4) and a vertical FET discharge transistor (T5). The drain terminals of the two control transistors are connected to the gate of the separating transistor (T6). The drain terminal of the discharge transistor is connected to the word line (WL). The source terminal of the first control transistor is at operational potential, while the source terminals of the second control transistor and the discharge transistor are at substrate biased potential.