Delay circuit for railway signalling systems - has clock-controlled shift registers in loop-circuit, which produce output signal within set delay time after being triggered

摘要

The delay circuit produces an output signal within a required time after the appearance of a trigger pulse. To keep the number of components to a min. the circuit employs two clock-controlled shift registers with a given number of stages in the loop circuit. When a trigger pulse appears only one register stage in each shift register is set into a given binary state. The output signals of the shift registers are processed in a logic circuit that controls a bistable flipflop.