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Parity prediction circuit for adder/counter
Parity prediction circuit for adder/counter
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机译:加法器/计数器的奇偶校验预测电路
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摘要
A parity prediction circuit for predicting parity in an adder, counter or similar device. The parity prediction is obtained with a parity prediction network connected from most significant bit to least significant bit. The parity prediction network is used in place of a parity generator or in combination with a parity generator for error checking purposes. In a special application, the parity prediction is employed for a ripple-carry type counter where the predicted parity bit is produced by a single network of NAND gates connected in series from high-order to low-order counter bits. The predicted parity is available no later than the completion of the carry-out propagation.
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