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Verification of logic circuits using Mizar and its application to an adder circuit on a radix-$2^k$SD number (Topics in Information Sciences and Applied Functional Analysis)

机译：使用Mizar验证逻辑电路并将其应用于基数为$ 2 ^ k $ SD的加法器电路（信息科学和应用功能分析的主题）

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作者
Shimizu Hidetaka; Nakamura Yatsuka; Fujisawa Yoshinori; Fuwa Yasushi;
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年度 2001
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原文格式 PDF
正文语种 en
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Verification of logic circuits using Mizar and its application to an adder circuit on a radix-$2^k$SD number (Topics in Information Sciences and Applied Functional Analysis)

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