PARITY PREDICTION CIRCUIT FOR FULL ADDER

摘要

PPROBLEM TO BE SOLVED: To construct a parity prediction circuit of a full adder from a small number of inputs and a small number of elements. PSOLUTION: The parity prediction circuit has computing units, each with a first selector which receives the inputs of carry four parity CP [k-1, 0] and CP [k-1, 1] when carry-in Cin=0 and 1 (k is an integer of not more than n) and which outputs either the input CP [k-1, 0] or CP [k-1, 1] as a carry four parity cp [k, 0] according to a generation bit g[k-2] resulting from addition inputs A[k-2] and B[k-2], and a second selector which receives the inputs of the carry four parity CP [k-1, 0] and CP [k-1, 1] and which outputs either the input CP [k-1, 0] or CP [k-1, 1] as an inverted signal of the carry four parity cp [k, 1] according to a propagation bit p [k-2] resulting from the addition inputs A[k-2] and B[k-2]. The computing units are interconnected in a plurality of rows, and either the carry four parity cp [n, 0] or cp [n, 1] is output as a carry four parity CPn according to the carry in Cin at the final selector. PCOPYRIGHT: (C)2004,JPO&NCIPI