'Circuit arrangement for the speed error compensation in the case of administration for color video signals again or otherwise'

摘要

PURPOSE:To reduce a residual phase shift by equalizing the speed error of the time- axis variation of an input signal to the difference between errors before and after one horizontal scanning section, by making corrections by the difference value and its integral value, and by phase-modulating a clock pulse by the corrected integral value. CONSTITUTION:Reproduced video signal (a), while supplied to A/D converter 1, is applied to write clock and speed error generating circuit 2, which generates write clocks W, CK to write signal (a) in memory 3 by address signal A and clock W, CK. With read clock R, CK of read clock generator 5 and address signal A of circuit 4, memory 3 is read. This circuit 2 obtains speed errors DELTAV before and after one horizontal scanning section, stores them in speed error memory and reproducing circuit 7, and applies them as reproduced signal DELTAJ to phase modulator 8 under the address control of circuit 4. Then, clock R, CK is phase-modulated to reduce the residual phase shift.