Universal MOS logic gate - has source and drains on single implantation layer with output and inverter transistor grids forming unique zone

摘要

The gate comprises a load transistor whose source is connected to the grid of several control transistors. All the transistors have an integrated single channel MOS structure. The sources (44) and the drains (45) of the transistors (45) are formed on a first implantation level on a semiconductor substrate. The grids (43) of these switching transistors together with the grid of the load transistor (40) constitute a single zone situated on a second implantation level. The second and first levels are separated by a thin insulating layer. An ohmic contact is formed from the first to the second layer between the grid and the source of the load transistor (40), with the grid being formed by an end part of the single zone. The gate may perform a switching function, or may provide an (A for +B) output from inputs A and B respectively.