首页> 外国专利> Clock phase control method for a digital data receiving system, phase recovery circuit for carrying out this method and digital data receiving system comprising this circuit

Clock phase control method for a digital data receiving system, phase recovery circuit for carrying out this method and digital data receiving system comprising this circuit

机译:用于数字数据接收系统的时钟相位控制方法,用于执行该方法的相位恢复电路以及包括该电路的数字数据接收系统

摘要

method of adjusting the phase of the clock circuit (3) for the reception of digital data.which provides for the elimination of frequencies in excess of 1 / t (t = period of data transmission)then the evaluation of the phase difference to correct the offset of the clock of the estimates with the sign.an example of the implementation of the system and process includes low pass filtering circuit (1a) and an evaluation circuit (2) and which sets, in accordance with the process.the optimal decision of the second circuit (3) is placed at the outlet of the adaptive filter (4).;application: all systems for the reception of digital data transmitted in linear modulation.
机译:调整时钟电路(3)的相位以接收数字数据的方法,该方法可以消除超过1 / t的频率(t =数据传输的周期),然后评估相位差以进行校正该系统和过程的实现示例包括低通滤波电路(1a)和评估电路(2),并根据该过程进行设置。第二电路(3)的第一部分放置在自适应滤波器(4)的出口。应用:所有用于接收以线性调制方式发送的数字数据的系统。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号