Interface for microprocessor memory and speech synthesiser - comprises buffer memory loaded from microprocessor memory and using synthesiser clock to issue output

摘要

An interface (5) between a speech synthesiser (1) and a CPU (2) and memory (3) comprises a buffer memory. The CPU and memories communicate via a data bus (4) to which the initialisation inputs of the synthesiser are also connected. The phrases synthesised comprise a library of words stored in the CPU memory and which are transferred to the buffer memory. The synthesiser provides a clock signal (H) at a rate which equals its digital data input. This clock signal is applied to the buffer memory and also provides a shift control for the parallel to serial converter (6) between the buffer and synthesiser. These actions allow the speech synthesiser to receive data and provide a speech output at a rate which avoids introduction of dead time in the CPU activities.