Standalone Functional Verification of Multicore Microprocessor Memory Subsystem Units Based on Application of Memory Subsystem Models

摘要

The novel approach to functional verification of memory subsystem components of multicore microprocessors with multilevel memory organization are considered in this paper. Some benefits of application standalone simulation based verification are marked out. The approach is based on application of high-level memory subsystem model of microprocessor full-system simulator. It allows to build UVM based test system and do not develop reference model of the verified unit. The architecture of the test system and functions of its components are presented. The memory subsystem model with the build-in checker could help to find bugs during the simulation. The memory subsystem model of Elbrus microprocessor and the test system for L2-cache verification are described.