INPUT/OUTPUT INTERRUPTING PROCESSING SYSTEM OF MULTIPROCESSOR SYSTEM

摘要

PURPOSE:To reduce the number of connecting lines for connecting a controller and a processor, by providing a PSWC register for holding a copy of a program status word of each processor, in the controller. CONSTITUTION:An interrupting destination determining logical circuit 71 inputs the contents of PSWC registers 72-75, and an interrupting destination processor is determined from these contents. When an interrupting destination is determined, the circuit 71 outputs an interrupting destination processor number through an interrupting destination processor informing line 6, by which a designated processor executes an interrupting processing. Rewriting of the PWSC registers 72-75 is executed as mentioned below, when a program status word PSW which each processor 1-4 has been changed. That is to say, it is executed by inputting the contents of PSW registers 11-14 of each processor 1-4 to the inside of a controller 7 through a system data bus 5, and transferring it to the PSWC registers 72-75. In this way, the number of connecting lines between the controller 7 and the processors 1-4 can be reduced.