首页> 外国专利> Integrating analog-to-digital converter having digitally-derived offset error compensation and bipolar operation without zero discontinuity

Integrating analog-to-digital converter having digitally-derived offset error compensation and bipolar operation without zero discontinuity

机译:集成模数转换器,具有数模偏移误差补偿和双极性工作而无零间断

摘要

An analog-to-digital converter of the ramp-integrator type utilizing a special technique to reduce errors due to offset voltages. The integrator first is ramped up and then back to a reference level, by sequential application of opposite-polarity reference signals. A digital determination of net offset error then is made by comparing the total time of ramp-up-and-back with a fixed time period set by a clock generator. During the subsequent conversion operation, integration of the analog signal is controlled in accordance with the amount of net offset error so as to provide a feed-forward error correction. Integration is always in the same direction away from zero for analog signals of either polarity, thus avoiding the effects of discontinuity around zero input.
机译:斜坡积分器类型的模数转换器利用一种特殊技术来减少由于偏移电压引起的误差。通过顺序施加相反极性的参考信号,积分器首先被提升,然后返回参考水平。然后,通过将上升和下降的总时间与时钟发生器设置的固定时间段进行比较,来对净偏移误差进行数字确定。在随后的转换操作期间,根据净偏移误差的量来控制模拟信号的积分,以提供前馈误差校正。对于任一极性的模拟信号,积分始终在远离零的同一方向上进行,从而避免了零输入附近的不连续影响。

著录项

  • 公开/公告号JPS6058613B2

    专利类型

  • 公开/公告日1985-12-20

    原文格式PDF

  • 申请/专利权人 ANALOG DEVICES INC;

    申请/专利号JP19740083141

  • 发明设计人 AIBAA UORUDO;

    申请日1974-07-19

  • 分类号H03M1/52;G01D5/249;H03M1/00;

  • 国家 JP

  • 入库时间 2022-08-22 07:44:11

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