PURPOSE:To save power consumption and to reduce the scale of a circuit by providing an intermediate frequency multiplexer which adds the outputs of the 1st and the 2nd mixers to each other and obtaining a chirp signal of intermediate frequency from the intermediate frequency multiplexer. CONSTITUTION:An address counter 2 accesses addresses of ROMs 3 and 4 with clock pulses obtained from a clock oscillator 1 and parallel bit data read out of the ROMs 3 and 4 are latched by latch circuits 5 and 6 and then converted by D/A converters 7 and 8 from a cosine and a sine digital signal to analog signals respectively. Those two analog signals are used by the mixers 11 and 12 to modulate the output of a carrier oscillator 9 and the output of a pi/2 phase shifter 10 which shifts the output of the oscillator 9; and the modulation outputs are multiplexed by a hybrid 13, thereby obtaining a chirp signal after single side-band modulation on an output side. Thus, the power consumption is reduced and the circuit scale is also reduced.
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