Switched capacitor bilinear differential intergrator free from parasitic capacitance

摘要

1. An integrator circuit comprising switched capacitors and a symmetrically mounted differential amplifier (10) having an inverting input (A), a non-inverting input (A'), two outputs (S and S'), a feedback capacitor (C2), which is not switched and which is connected between one output (S) and the inverting input, an identical further feedback capacitor connected between the other output (S') and the non-inverting input (A'), characterized in that the circuit comprises a direct connection capacitor (C1) between a first circuit input (E) and the non-inverting input (A'), an identical further direct connection capacitor (C1) between a second circuit input (E') and the inverting input (A), a switched capacitor (2C1) connected between the first circuit input (E) and the inverting input (A) and an identical switched capacitor between the second circuit input (E') and the non-inverting input (A'), that the capacitance of each of the switched capacitors is twice the capacitance of each direct connection capacitor, that the capacitors are switched periodically according to two clock phases in such a way that during a first phase, the switched capacitors are connected in series between one circuit input and an amplifier input and that during the second phase, the capacitor plates are connected to an earth terminal of the circuit.