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NEW TECHNIQUES FOR THE DESIGN OF BILINEAR SWITCHED-CAPACITOR LADDER FILTERS.

机译:双线性开关电容器梯形滤波器设计的新技术。

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摘要

Switched-capacitor filters have become very popular in recent years. this popularity was prompted by the facts that they are fully integratable using MOS technology and they possess important characteristics such as small size, clock controlled frequency response, ease of manufacturing, etc., which are essential in practical applications.;Existence of delay-free loops in SC ladder filters is one of the major factors limiting the performance of these structures. Three general techniques to break up delay-free loops in bilinear SC lowpass filters are presented. These techniques are extended and generalized for bilinear SC highpass and lowpass ladder structures. A general comparison among all three techniques for each case is carried out and the advantages and drawbacks are discussed.;A variety of new input stages which are parasitic insensitive are presented. These stages are compatible with both the direct and structures without delay-free loops (SWDFL) realizations. Two of them also perform S/H function.;Two general techniques to replace toggle-SC's with parasitic-insensitive SC's in SWDFL realizations are suggested.;The purpose of this research is to introduce new techniques and to improve and modify the existing techniques for the design of bilinear SC ladder structures which are derived from doubly-terminated analog models.;A new design technique to obtain an even-order bilinear SC lowpass filter with the minimum possible required opamps is presented.;A novel technique is introduced for the design of odd-order completely-parasitic insensitive SC highpass ladder filters. A new input stage is presented which also performs the S/H function in these structures. The design technique is extended to the even-order case.;For moderate to very wideband bandpass filters, a new design technique is presented which is based on a pseudo-N-path concept. The number of required opamps is reduced to half at the cost of increasing the number of the clock phases.;The computer program SCAR is utilized to verify the design techniques and also to find the sensitivities of the filters to element values and the finite gains of opamps.
机译:近年来,开关电容器滤波器已变得非常流行。它们之所以流行,是因为它们可以使用MOS技术完全集成,并且具有重要的特性,例如小尺寸,时钟控制的频率响应,易于制造等,这在实际应用中必不可少。 SC梯形滤波器中的环路是限制这些结构性能的主要因素之一。提出了三种打破双线性SC低通滤波器中无延迟环路的通用技术。这些技术针对双线性SC高通和低通梯形结构进行了扩展和推广。在每种情况下对这三种技术进行了一般比较,并讨论了其优缺点。提出了多种对寄生不敏感的新输入级。这些阶段与直接和无延迟循环(SWDFL)实现的结构兼容。他们中的两个还执行S / H功能。建议在SWDFL实现中用寄生不敏感的SC替换双态SC的两种通用技术。本研究的目的是介绍新技术,并对现有技术进行改进和修改。从双端模拟模型推导的双线性SC梯形结构的设计。;提出了一种新的设计技术,该技术获得了所需运放最少的偶数双线性SC低通滤波器。;介绍了一种新颖的设计技术奇数阶完全寄生不敏感SC高通梯形滤波器。提出了一个新的输入阶段,它也在这些结构中执行S / H功能。该设计技术扩展到偶数情况。对于中等到非常宽带的带通滤波器,提出了一种基于伪N路径概念的新设计技术。所需的运算放大器数量减少了一半,以增加时钟相位的数量为代价。计算机程序SCAR用于验证设计技术,还可以找到滤波器对元件值的敏感度和有限增益。运算放大器。

著录项

  • 作者

    HEDAYATI, ABDOLREZA.;

  • 作者单位

    University of California, Los Angeles.;

  • 授予单位 University of California, Los Angeles.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 1984
  • 页码 407 p.
  • 总页数 407
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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