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High performance bipolar transistor having a lightly doped guard ring disposed between the emitter and the extrinsic base region

机译:高性能双极晶体管,在发射极和非本征基极区之间设有轻掺杂的保护环

摘要

The present invention relates to a novel semiconductor device, such for example, an NPN bipolar transistor including a standard highly doped N+ emitter (28) separated on its sidewalls fom the P+ extrinsic base region (29) (base contact reach through) by a guard ring shaped region (30) having a significantly lower impurity concentration than the emitter (e.g. N-). Said region (30) is located beneath an insulating spacer (25).;The initial steps of the process are basically standard. The extrinsic base (29) is formed from a boron doped polysilicon contact region (16). The N* emitter region (28) is self aligned with the P+ polysilicon contact region (16), and remains separated thereof by said N region (30). The N+ emitter (28) is formed either using ion implantation techniques or a doped emitter polysilicon contact region. However, according to the teachings of the present invention, the intrinsic base (22) of the transistor is formed in situ, by a low dose low energy P type ion implantation through a mask, made with its concentration peak below the device surface. Subsequently, an intermediate N- region is formed by implanting N type impurities through the same mask just to convert superficially the conductivity of the top surface above the P intrinsic base into N type. The N+ emitter may be then formed in such a way it is separated from the extrinsic base by a guard ring shaped portion (30) of said lightly doped intermediate N- region. The transistor thus formed will have a controllable narrow base width and optimized concentration, and will exhibit desired low external resistance through the extrinsic base region. Both factors are essential to provide high speed and low power devices.;In addition, this transistor has a significantly high β factor (in the range of 150) with a limited modulation of said gain factor; it has also good Emitter-Base breakdown voltages (in the range of 6V).;Lastly, it presents increased inverse β which is a highly desirable factor for Merged Transistor Logic (MTL) applications.
机译:本发明涉及一种新颖的半导体器件,例如NPN双极晶体管,其包括在其侧壁上与P + + 发射极(28)。 >非本征基极区(29)(基极接触穿过),其保护环区域(30)的杂质浓度明显低于发射极(例如N -)。所述区域(30)位于绝缘隔离物(25)下方。该过程的初始步骤基本上是标准的。非本征基极(29)由掺硼的多晶硅接触区(16)形成。 N * 发射极区(28)与P + 多晶硅接触区(16)自对准,并保持与所述N区(30)隔开。使用离子注入技术或掺杂的发射极多晶硅接触区形成N + 发射极(28)。然而,根据本发明的教导,通过低剂量低能P型离子注入通过掩模原位形成晶体管的本征基极(22),使其浓度峰值低于器件表面。随后,通过将N型杂质通过相同的掩模注入而形成中间N -区域,只是将P本征基底上方的顶表面的电导率表面转化为N型。然后可以以这样的方式形成N + 发射极,使其通过所述轻掺杂中间N -区域的保护环形部分(30)与非本征基极分开。 。如此形成的晶体管将具有可控制的窄基极宽度和最佳浓度,并且将通过非本征基极区域表现出期望的低外部电阻。这两个因素对于提供高速和低功率器件都是必不可少的。此外,该晶体管具有很高的β因子(在150的范围内),并且对所述增益因子的调制受到限制。它具有良好的发射极-基极击穿电压(在6V范围内)。最后,它的反β增大,这是合并晶体管逻辑(MTL)应用中非常需要的因素。

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