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Universally testable logic elements and method for structural testing of logic circuits formed of such logic elements
Universally testable logic elements and method for structural testing of logic circuits formed of such logic elements
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机译:通用测试逻辑元件以及由这种逻辑元件形成的逻辑电路的结构测试方法
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摘要
The design of a universally testable logic element from which combinational and sequential logic circuits can be formed is disclosed. The logic element is designed to operate as a NAND gate, NOR gate, or other functionally complete logic function in its normal mode. In a first test mode, the element functions like an OR gate. In a second test mode, the element functions like an AND gate. By building a circuit with such a logic element, the circuit can be tested for all classical stuck-at-zero and stuck-at-one faults with a minimal number of test patterns. Methods of testing both combinational and sequential circuits formed from such logic elements are also disclosed.
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