首页> 外国专利> Universally testable logic elements and method for structural testing of logic circuits formed of such logic elements

Universally testable logic elements and method for structural testing of logic circuits formed of such logic elements

机译:通用测试逻辑元件以及由这种逻辑元件形成的逻辑电路的结构测试方法

摘要

The design of a universally testable logic element from which combinational and sequential logic circuits can be formed is disclosed. The logic element is designed to operate as a NAND gate, NOR gate, or other functionally complete logic function in its normal mode. In a first test mode, the element functions like an OR gate. In a second test mode, the element functions like an AND gate. By building a circuit with such a logic element, the circuit can be tested for all classical stuck-at-zero and stuck-at-one faults with a minimal number of test patterns. Methods of testing both combinational and sequential circuits formed from such logic elements are also disclosed.
机译:公开了一种通用的可测试逻辑元件的设计,可以从其形成组合和顺序逻辑电路。逻辑元件被设计为在其正常模式下用作“与非”门,“或非”门或其他功能上完整的逻辑功能。在第一测试模式下,该元件的功能类似于“或”门。在第二测试模式下,该元件的功能类似于“与”门。通过用这种逻辑元件构建电路,可以用最少数量的测试模式对电路进行所有经典的零卡和一卡故障的测试。还公开了测试由这种逻辑元件形成的组合电路和顺序电路的方法。

著录项

  • 公开/公告号US4625310A

    专利类型

  • 公开/公告日1986-11-25

    原文格式PDF

  • 申请/专利权人 MERCER;M. RAY;

    申请/专利号US19840602830

  • 发明设计人 M. RAY MERCER;

    申请日1984-04-23

  • 分类号G01R31/28;

  • 国家 US

  • 入库时间 2022-08-22 07:09:56

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