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Emitter coupled logic circuit with high drivability for capacitive load

机译:具有高可驱动性的发射极耦合逻辑电路,用于容性负载

摘要

An ECL (Emitter Coupled Logic) circuit is provided which has an increased ability to drive a large capacitive load or to drive a large fan-out circuit, wherein the power consumption per gate is reduced. The output circuit of the ECL circuit is provided with an emitter follower transistor which has the current therethrough detected by a detecting transistor. A current control transistor is provided to quickly charge the load capacitance under the control of the detecting transistor, and thus, the voltage drop of the output signal is improved. One of the emitter follower transistor and the current transistor are always cut off when the other is in a conductive state, and therefore, the current running through the circuit is reduced.
机译:提供了具有增强的驱动大电容负载或驱动大扇出电路的能力的ECL(发射极耦合逻辑)电路,其中每个门的功耗被降低。 ECL电路的输出电路设置有发射极跟随器晶体管,该发射极跟随器晶体管具有通过其中的电流被检测晶体管检测到。提供电流控制晶体管以在检测晶体管的控制下对负载电容快速充电,因此,改善了输出信号的电压降。当发射极跟随器晶体管和电流晶体管中的一个处于导通状态时,它总是被截止,因此,流经电路的电流减小了。

著录项

  • 公开/公告号US4678942A

    专利类型

  • 公开/公告日1987-07-07

    原文格式PDF

  • 申请/专利权人 FUJITSU LIMITED;

    申请/专利号US19850779356

  • 发明设计人 YASUNORI KANAI;TAICHI SAITOH;

    申请日1985-09-23

  • 分类号H03K19/01;H03K19/086;

  • 国家 US

  • 入库时间 2022-08-22 07:08:59

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