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Logic coincidence gate and logic sequential circuits using said coincidence gate

机译:逻辑符合门和使用所述符合门的逻辑时序电路

摘要

The invention relates to a coincidence gate, whose output only changes state if the inputs are of the same logic level. It has two parallel- connected NOT circuits, each constituted by a transistor, whose source is at earth and the drain supplied by a resistor, the gates constituting the inputs of the gate. The two resistors are identical saturated resistors and the first NOT circuit is supplied from a fixed voltage, whereas the second NOT circuit is supplied across a Schottky diode connected in the forward direction from the point common to the first saturated resistor and to the drain of the first transistor. The point common to the Schottky diode and the second saturated resistor constitutes the output of the coincidence gate. Application to sequential logic circuits.
机译:本发明涉及一种巧合门,它的输出仅在输入具有相同逻辑电平时才改变状态。它具有两个并联的NOT电路,每个电路由一个晶体管组成,其源极接地,其漏极由电阻器提供,栅极构成栅极的输入。这两个电阻是相同的饱和电阻,第一个NOT电路由固定电压供电,而第二个NOT电路跨接在肖特基二极管两端,肖特基二极管从与第一个饱和电阻和公共端之间的公共点开始正向连接。第一晶体管。肖特基二极管和第二个饱和电阻器的公共点构成了同步门的输出。适用于顺序逻辑电路。

著录项

  • 公开/公告号US4703204A

    专利类型

  • 公开/公告日1987-10-27

    原文格式PDF

  • 申请/专利权人 THOMSON-CSF;

    申请/专利号US19850807731

  • 发明设计人 NGU T. PHAM;

    申请日1985-12-11

  • 分类号H03K19/017;H03K19/02;H03K19/094;H03K19/092;

  • 国家 US

  • 入库时间 2022-08-22 07:08:30

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